3维超大规模集成电路：2.5集成方案（英文版）
出版时间：2010年版
内容简介
本书提出一种新的3维超大规模电路集成方案，即2．5维集成。根据这一集成方案实现的电子系统将由多层单片集成芯片叠加而成，芯片间将由极细小尺度的“垂直联线”实现电气连接。这一新集成方案能够在很大程度上克服积累成品率损失的问题。本书从制造成本和设计系统性能两方面探讨2．5维集成的可行性。首先，作者建立了一个成本分析模型来比较各种典型集成方案，分析数据表明2．5维集成具备制造成本上的优越性。从设计性能角度，作者完成了全定制和专用集成电路两种设计风格的一系列设计实例研究，从而证明了2．5维集成能够实现传统单片集成不能达到的系统性能。同时，为了实现2．5维／3维集成电路版图，作者也开发了第一代2．5维／3维物理设计EDA工具。本书适合集成电路工艺开发人员和决策人士、集成电路设计人员、电子设计自动化研发人员和决策人士参考。
目录
List of Figures and Tables
Introduction
1.1 2.5-D Integration
1.2 Enabling Technologies
1.2.1 Fabrication Technology
1.2.2 Testing Methodology and Fault Tolerance Technique
1.2.3 Design Technology
1.3 Objectives and Book Organization
References
A Cost Comparison of VLSI Integration Schemes
2.1 Non-Monolithic Integration Schemes
2.1.1 Multiple-Reticle Wafer
2.1.2 Multiple Chip Module (MCM)
2.1.3 Three-Dimensional (3-D) integration
2.2 Yield Analysis of Different VLSI Integration Approaches
2.2.1 Monolithic Soc
2.2.2 Multiple-Reticle Wafer (MRW)
2.2.3 Three-Dimensional (3-D) Integration
2.2.4 2.5-D System Integration
2.2.5 Multi-Chip Module
2.2.6 Summing Up
2.3 Observations
References
3 Design Case Studies
3.1 Crossbar
3.2 A 2.5-D Rambus DRAM Architecture
3.2.1 Tackle the Long Bus Wire
3.2.2 Serialized Channel in the 3rd Dimension
3.3 A2.5-D Redesign of PipeRench
3.3.1 The 2.5-D Implementation
3.3.2 Simulation Results
3.4 A2.5-D Integrated Microprocessor System
3.4.1 A 2.5-D Integrated Microprocessor System
3.4.2 An Analytical Performance Model
3.4.3 Detailed Performance Simulation for Reduced Memory Latency
3.5 Observations
References
4 An Automatic 2.5-D Layout Design Flow
4.1 A 2.5-D Layout Design Framework
4.1.1 2.5-D Floorplanning
4.1.2 2.5-D Placement
4.1.3 2.5-D Global Routing
4.2 'Observations
References
Fioorplanning for 2.5-D Integration
5.1 Floorplan Level Evaluation--Category 2 Circuits
5.1.1 Technique
5.1.2 Results
5.2 Floorplan Level Evaluation--Category 3 Circuits
5.2.1 Technique
5.2.2 Results
5.3 Thermal driven floorplanning
5.3.1 Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning
5.3.2 Coupled Temperature and Leakage Estimation
5.3.3 2.5-D Thermal Driven Floorplanning Techniques
5.3.4 Experimental results
5.4 Observations
References
Placement for 2.5-D Integration
6.1 Pure Standard Cell Designs
6.1.1 Placement Techniques
6.1.2 Benchmarks and Layout Model
6.1.3 Evaluation of Vertical Partitioning Strategies
6.1.4 Wire length scaling
6.1.5 Wire length reduction
6.1.6 Wire Length vs. Inter-Chip Contact Pitch
6.2 Mixed Macro and Standard Cell Designs
6.2.1 Placement Techniques
6.2.2 Results and Analysis
6.3 Observatiohs
References
A Road map of 2.5-D Integration
7.1 Stacked Memory
7.2 DRAM Integration for Bandwidth-Demanding Applications
7.3 Hybrid System Integration
7.4 Extremely High Performance Systems
7.4.1 Highly Integrated Image Sensor System
7.4.2 Radar-in-Cubc
References
Conclusion and Future Work
8.1 Main Contributions and Conclusions
8.2 Future Work
8.2.1 Fabrication Technology for 2.5-D Systems
8.2.2 Testing Techniques for 2.5-D Integration
8.2.3 Design Technology for 2.5-D Integration
References
Index
